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authorAlex Deucher <alexander.deucher@amd.com>2016-02-04 12:23:43 -0500
committerAlex Deucher <alexander.deucher@amd.com>2016-02-04 12:23:43 -0500
commitc5da5eade0b5769fce40f79fbad9153ea760b954 (patch)
tree21c3c1423b298509bd5acda94de0ca91c10665db
parent8be79be0433ba64c4674c3394b3fc8cbc33c46af (diff)
downloadlibdrm-c5da5eade0b5769fce40f79fbad9153ea760b954.tar.gz
libdrm-c5da5eade0b5769fce40f79fbad9153ea760b954.tar.xz
tests/amdgpu: make amdgpu_command_submission_sdma_write_linear generic
So it can be shared for CP tests. Reviewed-by: Ken Wang <Qingqing.Wang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
-rw-r--r--tests/amdgpu/basic_tests.c27
1 files changed, 18 insertions, 9 deletions
diff --git a/tests/amdgpu/basic_tests.c b/tests/amdgpu/basic_tests.c
index df5f5bc..6f238bc 100644
--- a/tests/amdgpu/basic_tests.c
+++ b/tests/amdgpu/basic_tests.c
@@ -49,6 +49,8 @@ static void amdgpu_command_submission_sdma(void);
static void amdgpu_userptr_test(void);
static void amdgpu_semaphore_test(void);
+static void amdgpu_command_submission_write_linear_helper(unsigned ip_type);
+
CU_TestInfo basic_tests[] = {
{ "Query Info Test", amdgpu_query_info_test },
{ "Memory alloc Test", amdgpu_memory_alloc },
@@ -619,7 +621,7 @@ static void amdgpu_test_exec_cs_helper(amdgpu_context_handle context_handle,
CU_ASSERT_EQUAL(r, 0);
}
-static void amdgpu_command_submission_sdma_write_linear(void)
+static void amdgpu_command_submission_write_linear_helper(unsigned ip_type)
{
const int sdma_write_length = 128;
const int pm4_dw = 256;
@@ -669,16 +671,18 @@ static void amdgpu_command_submission_sdma_write_linear(void)
/* fullfill PM4: test DMA write-linear */
i = j = 0;
- pm4[i++] = SDMA_PACKET(SDMA_OPCODE_WRITE,
- SDMA_WRITE_SUB_OPCODE_LINEAR, 0);
- pm4[i++] = 0xffffffff & bo_mc;
- pm4[i++] = (0xffffffff00000000 & bo_mc) >> 32;
- pm4[i++] = sdma_write_length;
- while(j++ < sdma_write_length)
- pm4[i++] = 0xdeadbeaf;
+ if (ip_type == AMDGPU_HW_IP_DMA) {
+ pm4[i++] = SDMA_PACKET(SDMA_OPCODE_WRITE,
+ SDMA_WRITE_SUB_OPCODE_LINEAR, 0);
+ pm4[i++] = 0xffffffff & bo_mc;
+ pm4[i++] = (0xffffffff00000000 & bo_mc) >> 32;
+ pm4[i++] = sdma_write_length;
+ while(j++ < sdma_write_length)
+ pm4[i++] = 0xdeadbeaf;
+ }
amdgpu_test_exec_cs_helper(context_handle,
- AMDGPU_HW_IP_DMA, 0,
+ ip_type, 0,
i, pm4,
1, resources,
ib_info, ibs_request);
@@ -705,6 +709,11 @@ static void amdgpu_command_submission_sdma_write_linear(void)
CU_ASSERT_EQUAL(r, 0);
}
+static void amdgpu_command_submission_sdma_write_linear(void)
+{
+ amdgpu_command_submission_write_linear_helper(AMDGPU_HW_IP_DMA);
+}
+
static void amdgpu_command_submission_sdma_const_fill(void)
{
const int sdma_write_length = 1024 * 1024;