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authorAlex Deucher <alexander.deucher@amd.com>2016-02-03 18:38:50 -0500
committerAlex Deucher <alexander.deucher@amd.com>2016-02-04 12:24:15 -0500
commit7c656ba72fb9f004c2bd6b578fe68966d9ef9118 (patch)
tree107f8eba869b78185054a92a75e94afddf5d12d1
parent47c7e7a6dd92c7c60c899b7103cf2a4457f83936 (diff)
downloadlibdrm-7c656ba72fb9f004c2bd6b578fe68966d9ef9118.tar.gz
libdrm-7c656ba72fb9f004c2bd6b578fe68966d9ef9118.tar.xz
tests/amdgpu: make amdgpu_command_submission_sdma_const_fill generic
So it can be shared for CP tests. Reviewed-by: Ken Wang <Qingqing.Wang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
-rw-r--r--tests/amdgpu/basic_tests.c24
1 files changed, 16 insertions, 8 deletions
diff --git a/tests/amdgpu/basic_tests.c b/tests/amdgpu/basic_tests.c
index dbfcfff..3e54787 100644
--- a/tests/amdgpu/basic_tests.c
+++ b/tests/amdgpu/basic_tests.c
@@ -50,6 +50,7 @@ static void amdgpu_userptr_test(void);
static void amdgpu_semaphore_test(void);
static void amdgpu_command_submission_write_linear_helper(unsigned ip_type);
+static void amdgpu_command_submission_const_fill_helper(unsigned ip_type);
CU_TestInfo basic_tests[] = {
{ "Query Info Test", amdgpu_query_info_test },
@@ -839,7 +840,7 @@ static void amdgpu_command_submission_sdma_write_linear(void)
amdgpu_command_submission_write_linear_helper(AMDGPU_HW_IP_DMA);
}
-static void amdgpu_command_submission_sdma_const_fill(void)
+static void amdgpu_command_submission_const_fill_helper(unsigned ip_type)
{
const int sdma_write_length = 1024 * 1024;
const int pm4_dw = 256;
@@ -888,15 +889,17 @@ static void amdgpu_command_submission_sdma_const_fill(void)
/* fullfill PM4: test DMA const fill */
i = j = 0;
- pm4[i++] = SDMA_PACKET(SDMA_OPCODE_CONSTANT_FILL, 0,
- SDMA_CONSTANT_FILL_EXTRA_SIZE(2));
- pm4[i++] = 0xffffffff & bo_mc;
- pm4[i++] = (0xffffffff00000000 & bo_mc) >> 32;
- pm4[i++] = 0xdeadbeaf;
- pm4[i++] = sdma_write_length;
+ if (ip_type == AMDGPU_HW_IP_DMA) {
+ pm4[i++] = SDMA_PACKET(SDMA_OPCODE_CONSTANT_FILL, 0,
+ SDMA_CONSTANT_FILL_EXTRA_SIZE(2));
+ pm4[i++] = 0xffffffff & bo_mc;
+ pm4[i++] = (0xffffffff00000000 & bo_mc) >> 32;
+ pm4[i++] = 0xdeadbeaf;
+ pm4[i++] = sdma_write_length;
+ }
amdgpu_test_exec_cs_helper(context_handle,
- AMDGPU_HW_IP_DMA, 0,
+ ip_type, 0,
i, pm4,
1, resources,
ib_info, ibs_request);
@@ -923,6 +926,11 @@ static void amdgpu_command_submission_sdma_const_fill(void)
CU_ASSERT_EQUAL(r, 0);
}
+static void amdgpu_command_submission_sdma_const_fill(void)
+{
+ amdgpu_command_submission_const_fill_helper(AMDGPU_HW_IP_DMA);
+}
+
static void amdgpu_command_submission_sdma_copy_linear(void)
{
const int sdma_write_length = 1024;